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CPU/FSB/Clock Cycle/ memory address question


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realitytripz

realitytripz

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Hello all I am brand new here to these forums and looking for some good insight. I have just finshed my A+ training but unfortunately there is alot of details that were left out or not explained very well.

I know the effective FSB is going to be the base system clock X 4 (quad-pumped) in an intel processor P4 and above.

So if that means that the FSB can handle 4 data signals per clock cycle, I am trying to under stand how the data is flowing.

In a 32-bit system does that mean 32-bits of data are sent 4 separate times during a clock cycle? I understand 32-bits is going to be the bandwith of the bus, but I just can't seem to get it straight.

I know that when data is sent through its really just electrons moving through circuits. But when a data signal is sent is it only going to be 32-bits wide or is the amount of data the signal is carrying only 32-bits? For example, 1 lane in my PCI express can move 250MB/s. Is that 250MB/s broken up into 32 bit increments and sent until all of it has gone?

Also another question I have is with memory addressing. A CPU will read from or write to memory addresses. In a 32-bit system, I understand each memory address is 32-bits wide? and if you do 2 to the power of 32 you get that 4billion+ number. So is that 4 billion+ different addresses?

Please help anyone! I will be eternally grateful!
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